synthesizable model

synthesizable model
синтезируемая модель
модель, например в языке VHDL, входящая в библиотеку синтезируемых подсистем; позволяет разработчику использовать её для взаимодействия с несинтезируемыми подсистемами. В синтезируемой модели проектируемой системы подсистемы заменяются сигналами, выдаваемыми на внешние аппаратные средства

Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. . 1998-2007.

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